- The lack of deterministic, high-efficiency photonic entanglement and loss-tolerant architectures suitable for fault-tolerant scaling - The absence of a standardised, integrated control stack combining photonic hardware, firmware, and system software with reliable benchmarking across platforms - By 2028, demonstration of a photonic NISQ processor with ≥100 photonic qubits, integrating deterministic single-photon sources, low-loss waveguides, on-chip detectors, and a firmware stack (scheduler, controller, compiler), validated via hardware-agnostic benchmarks and hybrid photonic-HPC application…
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Eligibility checkGrant from URBAN PROSUMERS (EU-funded project) across the EU. Total budget €180,000. Applications until 30 September 2026.
- Complete Indicator Framework: A validated indicator framework of short-term actions, outcomes and long-term impacts, for both the ECS programme and the Chips for Europe Initiative, integr…
This topic is the first phase of a two-phase competitive structure supported by Horizon Europe, implemented via a Coordination and Support Action (CSA) in close collaboration with the Europ…
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